Fairchild F8 (F3850/MK3870) opcode table
| x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | |
|---|---|---|---|---|---|---|---|---|
| 0x |
LRLoad Register A8-bit accumulator AKUScratchpad register 12
1
1
-----
|
LRLoad Register A8-bit accumulator AKLScratchpad register 13
1
1
-----
|
LRLoad Register A8-bit accumulator AQUScratchpad register 14
1
1
-----
|
LRLoad Register A8-bit accumulator AQLScratchpad register 15
1
1
-----
|
LRLoad Register KUScratchpad register 12A8-bit accumulator A
1
1
-----
|
LRLoad Register KLScratchpad register 13A8-bit accumulator A
1
1
-----
|
LRLoad Register QUScratchpad register 14A8-bit accumulator A
1
1
-----
|
LRLoad Register QLScratchpad register 15A8-bit accumulator A
1
1
-----
|
| 1x |
LRLoad Register KScratchpad registers 12 (KU) and 13 (KL)P16-bit stack register (PC1)
1
4
-----
|
LRLoad Register P16-bit stack register (PC1)KScratchpad registers 12 (KU) and 13 (KL)
1
4
-----
|
LRLoad Register A8-bit accumulator AIS6-bit Indirect Scratchpad Address Register (ISAR)
1
1
-----
|
LRLoad Register IS6-bit Indirect Scratchpad Address Register (ISAR)A8-bit accumulator A
1
1
-----
|
PKCall subroutine in K
1
2.5
-----
|
LRLoad Register P0Program Counter (PC0)QScratchpad registers 14 (QU) and 15 (QL)
1
4
-----
|
LRLoad Register HScratchpad registers 10 (HU) and 11 (HL)DCData Counter (DC0)
1
4
-----
|
LRLoad Register QScratchpad registers 14 (QU) and 15 (QL)DCData Counter (DC0)
1
4
-----
|
| 2x |
LRLoad Register DCData Counter (DC0)QScratchpad registers 14 (QU) and 15 (QL)
1
4
-----
|
LRLoad Register HScratchpad registers 10 (HU) and 11 (HL)DCData Counter (DC0)
1
4
-----
|
SRShift Right 1Constant number
1
1
-0Z01
|
SLShift Left 1Constant number
1
1
-0Z0S
|
SRShift Right 4Constant number
1
1
-0Z01
|
SLShift Left 4Constant number
1
1
-0Z0S
|
LMLoad A from Memory (DC0)
1
2.5
-----
|
STStore A to memory (DC0)
1
2.5
-----
|
| 3x |
COMComplement A
1
1
-0Z0S
|
LNKAdd (Link) carry flag to A
1
1
-OZCS
|
DIDisable Interrupt
1
1
0----
|
EIEnable Interrupt
1
1
1----
|
POPReturn from subroutine
1
2
-----
|
LRLoad Register WStatus registerJScratchpad register 9
1
1
-----
|
LRLoad Register WStatus registerJScratchpad register 9
1
2
-----
|
INCIncrement A
1
1
-OZCS
|
| 4x |
LILoad Immediate d88-bit immediate value
2
2.5
-----
|
NIAND A with Immediate d88-bit immediate value
2
2.5
-0Z0S
|
OIOR A with Immediate d88-bit immediate value
2
2.5
-0Z0S
|
XIXOR A with Immediate d88-bit immediate value
2
2.5
-0Z0S
|
AIAdd immediate to A d88-bit immediate value
2
2.5
-OZCS
|
CICompare Immediate d88-bit immediate value
2
2.5
-OZCS
|
INInput port with long address to A d88-bit immediate value
2
4
-0Z0S
|
OUTOutput A to port with long address d88-bit immediate value
2
4
-----
|
| 5x |
PICall subroutine Immediate (changes A) d1616-bit immediate value
3
6.5
-----
|
JMPJump immediate d1616-bit immediate value
3
5.5
-----
|
DCILoad DC Immediate d1616-bit immediate value
3
6
-----
|
NOPNo Operation
1
1
-----
|
XDCExchange Data Counters (swap DC0 and DC1)
1
2
-----
|
NOPNo Operation
(illegal opcode) 1 1 ----- |
NOPNo Operation
(illegal opcode) 1 1 ----- |
NOPNo Operation
(illegal opcode) 1 1 ----- |
| 6x |
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 0Scratchpad register 0
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 1Scratchpad register 1
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 2Scratchpad register 2
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 3Scratchpad register 3
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 4Scratchpad register 4
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 5Scratchpad register 5
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 6Scratchpad register 6
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 7Scratchpad register 7
1
1.5
-OZCS
|
| 7x |
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 8Scratchpad register 8
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 9Scratchpad register 9 (J)
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 10Scratchpad register 10 (HU)
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit 11Scratchpad register 11 (HL)
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit SScratchpad register addressed by ISAR. Also known as IS and 12.
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit IScratchpad register addressed by ISAR; ISAR is post-incremented. Also known as 13.
1
1.5
-OZCS
|
DSDecrement Scratchpad content; post-decrement ISAR's lower octal digit DScratchpad register addressed by ISAR; ISAR is post-decremented. Also known as 14.
1
1.5
-OZCS
|
NOPNo Operation
(illegal opcode) 1 1 ----- |
| 10x |
LRLoad Register A8-bit accumulator A0Scratchpad register 0
1
1
-----
|
LRLoad Register A8-bit accumulator A1Scratchpad register 1
1
1
-----
|
LRLoad Register A8-bit accumulator A2Scratchpad register 2
1
1
-----
|
LRLoad Register A8-bit accumulator A3Scratchpad register 3
1
1
-----
|
LRLoad Register A8-bit accumulator A4Scratchpad register 4
1
1
-----
|
LRLoad Register A8-bit accumulator A5Scratchpad register 5
1
1
-----
|
LRLoad Register A8-bit accumulator A6Scratchpad register 6
1
1
-----
|
LRLoad Register A8-bit accumulator A7Scratchpad register 7
1
1
-----
|
| 11x |
LRLoad Register A8-bit accumulator A8Scratchpad register 8
1
1
-----
|
LRLoad Register A8-bit accumulator A9Scratchpad register 9 (J)
1
1
-----
|
LRLoad Register A8-bit accumulator A10Scratchpad register 10 (HU)
1
1
-----
|
LRLoad Register A8-bit accumulator A11Scratchpad register 11 (HL)
1
1
-----
|
LRLoad Register A8-bit accumulator ASScratchpad register addressed by ISAR. Also known as IS and 12.
1
1
-----
|
LRLoad Register A8-bit accumulator AIScratchpad register addressed by ISAR; ISAR is post-incremented. Also known as 13.
1
1
-----
|
LRLoad Register A8-bit accumulator ADScratchpad register addressed by ISAR; ISAR is post-decremented. Also known as 14.
1
1
-----
|
NOPNo Operation
(illegal opcode) 1 1 ----- |
| 12x |
LRLoad Register 0Scratchpad register 0A8-bit accumulator A
1
1
-----
|
LRLoad Register 1Scratchpad register 1A8-bit accumulator A
1
1
-----
|
LRLoad Register 2Scratchpad register 2A8-bit accumulator A
1
1
-----
|
LRLoad Register 3Scratchpad register 3A8-bit accumulator A
1
1
-----
|
LRLoad Register 4Scratchpad register 4A8-bit accumulator A
1
1
-----
|
LRLoad Register 5Scratchpad register 5A8-bit accumulator A
1
1
-----
|
LRLoad Register 6Scratchpad register 6A8-bit accumulator A
1
1
-----
|
LRLoad Register 7Scratchpad register 7A8-bit accumulator A
1
1
-----
|
| 13x |
LRLoad Register 8Scratchpad register 8A8-bit accumulator A
1
1
-----
|
LRLoad Register 9Scratchpad register 9 (J)A8-bit accumulator A
1
1
-----
|
LRLoad Register 10Scratchpad register 10 (HU)A8-bit accumulator A
1
1
-----
|
LRLoad Register 11Scratchpad register 11 (HL)A8-bit accumulator A
1
1
-----
|
LRLoad Register SScratchpad register addressed by ISAR. Also known as IS and 12.A8-bit accumulator A
1
1
-----
|
LRLoad Register IScratchpad register addressed by ISAR; ISAR is post-incremented. Also known as 13.A8-bit accumulator A
1
1
-----
|
LRLoad Register DScratchpad register addressed by ISAR; ISAR is post-decremented. Also known as 14.A8-bit accumulator A
1
1
-----
|
NOPNo Operation
(illegal opcode) 1 1 ----- |
| 14x |
LISULoad ISAR, Upper octal digit 0Constant number
1
1
-----
|
LISULoad ISAR, Upper octal digit 1Constant number
1
1
-----
|
LISULoad ISAR, Upper octal digit 2Constant number
1
1
-----
|
LISULoad ISAR, Upper octal digit 3Constant number
1
1
-----
|
LISULoad ISAR, Upper octal digit 4Constant number
1
1
-----
|
LISULoad ISAR, Upper octal digit 5Constant number
1
1
-----
|
LISULoad ISAR, Upper octal digit 6Constant number
1
1
-----
|
LISULoad ISAR, Upper octal digit 7Constant number
1
1
-----
|
| 15x |
LISLLoad ISAR, Lower octal digit 0Constant number
1
1
-----
|
LISLLoad ISAR, Lower octal digit 1Constant number
1
1
-----
|
LISLLoad ISAR, Lower octal digit 2Constant number
1
1
-----
|
LISLLoad ISAR, Lower octal digit 3Constant number
1
1
-----
|
LISLLoad ISAR, Lower octal digit 4Constant number
1
1
-----
|
LISLLoad ISAR, Lower octal digit 5Constant number
1
1
-----
|
LISLLoad ISAR, Lower octal digit 6Constant number
1
1
-----
|
LISLLoad ISAR, Lower octal digit 7Constant number
1
1
-----
|
| 16x |
CLRClear A
1
1
-----
|
LISLoad Immediate Short 1Constant number
1
1
-----
|
LISLoad Immediate Short 2Constant number
1
1
-----
|
LISLoad Immediate Short 3Constant number
1
1
-----
|
LISLoad Immediate Short 4Constant number
1
1
-----
|
LISLoad Immediate Short 5Constant number
1
1
-----
|
LISLoad Immediate Short 6Constant number
1
1
-----
|
LISLoad Immediate Short 7Constant number
1
1
-----
|
| 17x |
LISLoad Immediate Short 8Constant number
1
1
-----
|
LISLoad Immediate Short 9Constant number
1
1
-----
|
LISLoad Immediate Short 10Constant number
1
1
-----
|
LISLoad Immediate Short 11Constant number
1
1
-----
|
LISLoad Immediate Short 12Constant number
1
1
-----
|
LISLoad Immediate Short 13Constant number
1
1
-----
|
LISLoad Immediate Short 14Constant number
1
1
-----
|
LISLoad Immediate Short 15Constant number
1
1
-----
|
| 20x |
BTAND operand mask with W and Branch if True 0Constant numberd88-bit immediate value
2
3
-----
|
BPBranch if Positive (S flag is set) d88-bit immediate value
2
3/3.5
-----
|
BCBranch if Carry (C flag is set) d88-bit immediate value
2
3/3.5
-----
|
BTAND operand mask with W and Branch if True 3Constant numberd88-bit immediate value
2
3/3.5
-----
|
BZBranch if Zero (Z flag is set) d88-bit immediate value
2
3/3.5
-----
|
BTAND operand mask with W and Branch if True 5Constant numberd88-bit immediate value
2
3/3.5
-----
|
BTAND operand mask with W and Branch if True 6Constant numberd88-bit immediate value
2
3/3.5
-----
|
BTAND operand mask with W and Branch if True 7Constant numberd88-bit immediate value
2
3/3.5
-----
|
| 21x |
AMAdd Memory (DC0) to A
1
2.5
-OZCS
|
AMDAdd memory (DC0) to A as decimal (BCD)
1
2.5
-0Z0S
|
NMAND A with Memory (DC0)
1
2.5
-0Z0S
|
OMOR A with Memory (DC0)
1
2.5
-0Z0S
|
XMXOR A with Memory (DC0)
1
2.5
-0Z0S
|
CMCompare Memory (DC0) to A
1
2.5
-----
|
ADCAdd A (signed) to DC0
1
2.5
-----
|
BR7Branch if the low octal digit of ISAR is not 7 d88-bit immediate value
2
3/3.5
-----
|
| 22x |
BRBranch unconditionally d88-bit immediate value
2
3.5
-----
|
BMBranch if Minus (S flag is reset) d88-bit immediate value
2
3/3.5
-----
|
BNCBranch if No Carry (C flag is reset) d88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 3Constant numberd88-bit immediate value
2
3/3.5
-----
|
BNZBranch if Not Zero (Z flag is reset) d88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 5Constant numberd88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 6Constant numberd88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 7Constant numberd88-bit immediate value
2
3/3.5
-----
|
| 23x |
BNOBranch if No Overflow (O flag is reset) d88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 9Constant numberd88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 10Constant numberd88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 11Constant numberd88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 12Constant numberd88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 13Constant numberd88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 14Constant numberd88-bit immediate value
2
3/3.5
-----
|
BFAND operand mask with W and Branch if False 15Constant numberd88-bit immediate value
2
3/3.5
-----
|
| 24x |
INSInput port with Short address to A 0Constant number
1
2
-0Z0S
|
INSInput port with Short address to A 1Constant number
1
2
-0Z0S
|
INSInput port with Short address to A 2Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 3Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 4Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 5Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 6Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 7Constant number
1
4
-0Z0S
|
| 25x |
INSInput port with Short address to A 8Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 9Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 10Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 11Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 12Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 13Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 14Constant number
1
4
-0Z0S
|
INSInput port with Short address to A 15Constant number
1
4
-0Z0S
|
| 26x |
OUTSOutput A to port with Short address 0Constant number
1
2
-----
|
OUTSOutput A to port with Short address 1Constant number
1
2
-----
|
OUTSOutput A to port with Short address 2Constant number
1
4
-----
|
OUTSOutput A to port with Short address 3Constant number
1
4
-----
|
OUTSOutput A to port with Short address 4Constant number
1
4
-----
|
OUTSOutput A to port with Short address 5Constant number
1
4
-----
|
OUTSOutput A to port with Short address 6Constant number
1
4
-----
|
OUTSOutput A to port with Short address 7Constant number
1
4
-----
|
| 27x |
OUTSOutput A to port with Short address 8Constant number
1
4
-----
|
OUTSOutput A to port with Short address 9Constant number
1
4
-----
|
OUTSOutput A to port with Short address 10Constant number
1
4
-----
|
OUTSOutput A to port with Short address 11Constant number
1
4
-----
|
OUTSOutput A to port with Short address 12Constant number
1
4
-----
|
OUTSOutput A to port with Short address 13Constant number
1
4
-----
|
OUTSOutput A to port with Short address 14Constant number
1
4
-----
|
OUTSOutput A to port with Short address 15Constant number
1
4
-----
|
| 30x |
ASAdd Scratchpad register to A 0Scratchpad register 0
1
1
-OZCS
|
ASAdd Scratchpad register to A 1Scratchpad register 1
1
1
-OZCS
|
ASAdd Scratchpad register to A 2Scratchpad register 2
1
1
-OZCS
|
ASAdd Scratchpad register to A 3Scratchpad register 3
1
1
-OZCS
|
ASAdd Scratchpad register to A 4Scratchpad register 4
1
1
-OZCS
|
ASAdd Scratchpad register to A 5Scratchpad register 5
1
1
-OZCS
|
ASAdd Scratchpad register to A 6Scratchpad register 6
1
1
-OZCS
|
ASAdd Scratchpad register to A 7Scratchpad register 7
1
1
-OZCS
|
| 31x |
ASAdd Scratchpad register to A 8Scratchpad register 8
1
1
-OZCS
|
ASAdd Scratchpad register to A 9Scratchpad register 9 (J)
1
1
-OZCS
|
ASAdd Scratchpad register to A 10Scratchpad register 10 (HU)
1
1
-OZCS
|
ASAdd Scratchpad register to A 11Scratchpad register 11 (HL)
1
1
-OZCS
|
ASAdd Scratchpad register to A SScratchpad register addressed by ISAR. Also known as IS and 12.
1
1
-OZCS
|
ASAdd Scratchpad register to A IScratchpad register addressed by ISAR; ISAR is post-incremented. Also known as 13.
1
1
-OZCS
|
ASAdd Scratchpad register to A DScratchpad register addressed by ISAR; ISAR is post-decremented. Also known as 14.
1
1
-OZCS
|
NOPNo Operation
(illegal opcode) 1 1 ----- |
| 32x |
ASDAdd Scratchpad register to A as Decimal (BCD) 0Scratchpad register 0
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 1Scratchpad register 1
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 2Scratchpad register 2
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 3Scratchpad register 3
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 4Scratchpad register 4
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 5Scratchpad register 5
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 6Scratchpad register 6
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 7Scratchpad register 7
1
2
-OZCS
|
| 33x |
ASDAdd Scratchpad register to A as Decimal (BCD) 8Scratchpad register 8
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 9Scratchpad register 9 (J)
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 10Scratchpad register 10 (HU)
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) 11Scratchpad register 11 (HL)
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) SScratchpad register addressed by ISAR. Also known as IS and 12.
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) IScratchpad register addressed by ISAR; ISAR is post-incremented. Also known as 13.
1
2
-OZCS
|
ASDAdd Scratchpad register to A as Decimal (BCD) DScratchpad register addressed by ISAR; ISAR is post-decremented. Also known as 14.
1
2
-OZCS
|
NOPNo Operation
(illegal opcode) 1 1 ----- |
| 34x |
XSXOR A with Scratchpad 0Scratchpad register 0
1
1
-0Z0S
|
XSXOR A with Scratchpad 1Scratchpad register 1
1
1
-0Z0S
|
XSXOR A with Scratchpad 2Scratchpad register 2
1
1
-0Z0S
|
XSXOR A with Scratchpad 3Scratchpad register 3
1
1
-0Z0S
|
XSXOR A with Scratchpad 4Scratchpad register 4
1
1
-0Z0S
|
XSXOR A with Scratchpad 5Scratchpad register 5
1
1
-0Z0S
|
XSXOR A with Scratchpad 6Scratchpad register 6
1
1
-0Z0S
|
XSXOR A with Scratchpad 7Scratchpad register 7
1
1
-0Z0S
|
| 35x |
XSXOR A with Scratchpad 8Scratchpad register 8
1
1
-0Z0S
|
XSXOR A with Scratchpad 9Scratchpad register 9 (J)
1
1
-0Z0S
|
XSXOR A with Scratchpad 10Scratchpad register 10 (HU)
1
1
-0Z0S
|
XSXOR A with Scratchpad 11Scratchpad register 11 (HL)
1
1
-0Z0S
|
XSXOR A with Scratchpad SScratchpad register addressed by ISAR. Also known as IS and 12.
1
1
-0Z0S
|
XSXOR A with Scratchpad IScratchpad register addressed by ISAR; ISAR is post-incremented. Also known as 13.
1
1
-0Z0S
|
XSXOR A with Scratchpad DScratchpad register addressed by ISAR; ISAR is post-decremented. Also known as 14.
1
1
-0Z0S
|
NOPNo Operation
(illegal opcode) 1 1 ----- |
| 36x |
NSAND A with Scratchpad register 0Scratchpad register 0
1
1
-0Z0S
|
NSAND A with Scratchpad register 1Scratchpad register 1
1
1
-0Z0S
|
NSAND A with Scratchpad register 2Scratchpad register 2
1
1
-0Z0S
|
NSAND A with Scratchpad register 3Scratchpad register 3
1
1
-0Z0S
|
NSAND A with Scratchpad register 4Scratchpad register 4
1
1
-0Z0S
|
NSAND A with Scratchpad register 5Scratchpad register 5
1
1
-0Z0S
|
NSAND A with Scratchpad register 6Scratchpad register 6
1
1
-0Z0S
|
NSAND A with Scratchpad register 7Scratchpad register 7
1
1
-0Z0S
|
| 37x |
NSAND A with Scratchpad register 8Scratchpad register 8
1
1
-0Z0S
|
NSAND A with Scratchpad register 9Scratchpad register 9 (J)
1
1
-0Z0S
|
NSAND A with Scratchpad register 10Scratchpad register 10 (HU)
1
1
-0Z0S
|
NSAND A with Scratchpad register 11Scratchpad register 11 (HL)
1
1
-0Z0S
|
NSAND A with Scratchpad register SScratchpad register addressed by ISAR. Also known as IS and 12.
1
1
-0Z0S
|
NSAND A with Scratchpad register IScratchpad register addressed by ISAR; ISAR is post-incremented. Also known as 13.
1
1
-0Z0S
|
NSAND A with Scratchpad register DScratchpad register addressed by ISAR; ISAR is post-decremented. Also known as 14.
1
1
-0Z0S
|
NOPNo Operation
(illegal opcode) 1 1 ----- |
Illegal/undocumented instructions
Stack, I/O and machine control instructions
Branch and program flow instructions
Data transfer instructions
Arithmetic instructions
Logical instructions
| INS op | ← | Instruction mnemonic | ||
| Length in bytes | → | 2 7 | ← | Cycles |
| IOZCS | ← | Flags affected |
Flag registers and their bit positions in W:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| - | - | - | I | O | Z | C | S |
- S: Sign flag; set to bit 7 of result
- C: Carry flag; set to carry out of bit 7 in result
- Z: Zero flag; set if the result was zero, reset otherwise
- O: Overflow flag (OVF); set to carry out of bit 6 in result
- I: Interrupt Control Bit (ICB)
- No flag, bit is always 0 in W
- No flag, bit is always 0 in W
- No flag, bit is always 0 in W
Flags affected are always shown in the W bit order: IOZCS. If a flag is marked by "0" it means it is reset after the instruction. If it is marked by "1" it is set. If it is marked by "-" it is not changed. If it is marked by its letter, the corresponding flag is affected by the instruction.
The duration of conditional calls and returns is different when the branch is taken or not. This is indicated by two numbers separated by “/”. The lower number (on the left side of “/”) is the duration of the instruction when there is no branch, and the higher number (on the right side of “/”) is the duration of the instruction when the branch is taken.
d8 immediate 8-bit data
d16 immediate 16-bit data
a16 16-bit address